The invention relates to digital television, and more particularly, to improving received signal quality when using multiple antennas in a diversity combine receiver.
A diversity combine architecture is often utilized when receiving digital television signals. The term diversity combine refers to employing a plurality of antennas being separated from each other to increase the chances of receiving a high quality signal. For example, diversity combine architectures are often utilized in automobile based television receivers. By using more than one antenna, the likelihood of at least one of the antennas receiving a higher quality signal is increased.
FIG. 1 shows a conventional diversity combine architecture 100 according to the related art. As shown in FIG. 1, the conventional diversity combine architecture 100 includes a master receiver 102 being coupled to a first antenna 101, and a slave receiver 104 being coupled to a second antenna 103. The master receiver 102 and the slave receiver 104 are typically each implemented by an integrated circuit (IC), where a video decoder such as an MPEG decoder 106 is coupled to the master receiver 102 but not the slave receiver 104. In this way, the actual number of antennas 101, 103 can be easily scaled to any number. That is, adding another antenna to the architecture simply involves adding another slave receiver IC being connected in the same manner to the first slave receiver 104.
In FIG. 1, the slave receiver 104 utilizes the demodulator 116 to demodulate a received signal and to correlate with channel state information (e.g., representative signal quality or reliability information). The received signal and channel state information is passed to the signal combine unit 110 of the master receiver 102 where further channel decoding and smooth buffer operations are performed. The goal of the smooth buffer 114 is to ensure that transport stream (TS) packets decoded from the received signal are passed to the MPEG decoder 106 at a uniform rate. By passing TS packets to the MPEG decoder 106 at a uniform rate, the MPEG decoder 106 is able to make a 27 MHz PLL in a subsequent stage lock at a very stable reference frequency according to the regular incrementing of the program clock reference (PCR). Having a stable reference frequency helps assure high quality overall picture frame quality. Should the smooth buffer be unable to pass TS packets to the MPEG decoder at a uniform rate, the 27 MHz PLL will not have a stable frequency and the resulting overall picture frame quality will suffer.
FIG. 2 shows degraded received signal quality and a resulting degraded synchronization clock reference signal of the master receiver 102 of FIG. 1. To perform the above described TS packet smoothing operation, the smooth buffer 114 requires that the demodulator 108 provides an accurate synchronization clock reference signal to allow the smooth buffer 114 to determine the uniform rate at which to pass packets to the MPEG decoder 106. However, in some situations the signal quality of the master receiver 102 will be very poor. For example, a poor signal quality of the master receiver 102 could be caused by a malfunction with the first antenna 101 or if an object blocks the signal reception of the first antenna 101 as shown in FIG. 2. In this type of situation, the demodulator 108 of the master receiver 102 will be unable to provide an accurate synchronization clock reference to the smooth buffer 114. The smooth buffer 114 will therefore be unable to operate normally. As previously mentioned, this will have a negative impact on overall picture frame quality. For example, the smooth buffer 114 may encounter a buffer overflow because of an improper rate of packets being passed from the smooth buffer 114 to the MPEG decoder 106. Buffer overflow will result in packet loss, which has a very serious negative effect on MPEG video decoding operations. An improved diversity receiver architecture that avoids this problem would be beneficial.